Balanced transformer-less amplifier and an offset detection and correction system therefore

ABSTRACT

A balanced transformer-less amplifier comprising a system for detecting and correcting DC offset across the output terminals of the amplifier. The output signal is digitized, preferably in a sigma delta modulator, the digitized signal is counted during a predetermined period and the result of the counting is used to derive a DC correction signal which is fed back to the input of the amplifier.

[0001] This invention relates to a balanced transformer-less (BTL)amplifier with output terminals for establishing a DC-connection to aload, comprising an offset detection system for detecting a differentialDC-offset across the output terminals. An amplifier of the abovementioned kind is known from the European patent application 1,006,650.

[0002] Presently, balanced transformer-less-amplifiers are often used,for instance in audio systems for driving loudspeakers. Anotherapplication is in systems for driving actuators. These amplifiers havethe advantage that they can generate large AC-power with low voltagepower supply and, because of the absence of output transformers or largeDC-separating capacitors, they can easily be implemented in integratedcircuit form. These advantages make them particularly useful as poweramplifiers for use in car-audio systems where they drive one or moreloudspeakers.

[0003] However, the consequence of the DC-connection between the outputterminals of the amplifier and the load, especially when this load has alow DC-impedance, is that large DC-currents may flow through the loadif, for whatever reason, a DC-offset voltage exists between the outputterminals of the amplifier. Such DC-offset voltage may e.g. be caused bya leaking DC-separation capacitor in the input of the amplifier or by anunbalance in the amplifier itself. The undesired DC-current, which mayflow through the load, may be so large that the amplifier or the load(e.g. loudspeakers) is damaged or even that a serious fire-hazardoccurs. In the balanced transformer-less-amplifier disclosed in theabove mentioned European patent application, these problems are solvedby said offset detection system, which then initializes an alarm systemin case the DC-offset voltage exceeds a predetermined level. This priorart system periodically mutes the amplifier input signal, then measuresthe DC-offset between the output terminals and, in case this DC-offsetexceeds the predetermined level, actuates an alarm system or even shutsoff the amplifier or disconnects the amplifier from the load.

[0004] The present invention seeks to provide an amplifier of the abovereferenced kind which has improved functionality and the amplifier ofthe present invention may therefore be characterized in that said offsetdetection system comprises an analog to digital converter to convert thesignal voltage across the output terminals into a digital signal, acounter integrating the digital signal during a predetermined period oftime, evaluation means for evaluating the result of said counter and adigital to analog converter to generate, in response to the output ofthe evaluation means, an analog correction signal which is applied tothe input of the amplifier for counteracting the DC-offset across theoutput terminals.

[0005] In the amplifier of the present invention the entire signalacross the output terminals, i.e. both the DC offset and the AC signal,is measured. This entire signal is digitized and counted during apredetermined sufficiently long period, so that the result of thecounting after the predetermined period is in essence only dependent onthe DC offset and not on the, for the measurement undesired, AC signal.The counting result may, after digital to analog conversion, be appliedto the input of the amplifier as a DC feedback to reduce the offset. Theamplifier of the invention dynamically reduces the DC offset, so thatthe dissipation in the load and in the amplifier output stages issubstantially reduced. This is of particular importance inbattery-operated amplifiers. Another advantage of the amplifier of thepresent invention is that the DC-offset measurement is carried outwithout interrupting the normal operation of the amplifier. Moreover,the digital solution is much more robust than analog integratingsystems, which must operate with very small and fragile currents inorder to be able to obtain usable time-constants at a reasonable chiparea.

[0006] A preferred balanced transformer-less-amplifier according to thepresent invention is characterized in that the analog to digitalconverter is a sigma-delta modulator generating a 1-bit digitalrepresentation of the signal voltage across the output terminals of theamplifier. The sigma delta modulator is a simple and straightforwardanalog to digital converter, which has the additional advantage that a1-bit digital representation of the analog signal is obtained which canbe directly supplied to the counter. The counter may e.g. be up countedby the one-bits and down counted by the zero-bits of the sigma-deltamodulator. However, because the counting period and the bit-rate arepredetermined, a simpler counter may be used in which the one bits onlycount upwards while the zero bits have no effect.

[0007] The output of the counter may be applied to a digital to analogconverter for generating a DC feedback signal for application to theinput of the amplifier. However, the count result still comprises ameasurement error which is caused by the incomplete cancellation of theAC component across the output terminals of the amplifier. Apparently,the count will be higher if the predetermined period ends when the ACsignal is high then if the predetermined period ends when the AC signalis low. To remove this distortion and to make the offset control systemresponding less instantaneously, the balanced transformer-less amplifierof the invention may be advantageously characterized in that theevaluation means are arranged to generate a first signal when the resultof the counter is above a first predetermined level and a second signalwhen the result of the counter is below a second predetermined level,which is lower than the first level, in that a correction counter isprovided which is decremented by a predetermined number when theevaluating means generate the first signal and which is incremented bysaid predetermined number when the evaluation means generate the secondsignal and in that the output of the correction counter is applied tosaid digital to analog converter.

[0008] The balanced transformer-less amplifier of the present inventionmay also be characterized in that the evaluation means are furtherarranged to generate a third signal when the result of the counter isabove a third predetermined level, which is higher than the first leveland a fourth signal when the result of the counter is below a fourthpredetermined level, which is lower than the second level and that alarmmeans are provided which are actuated when the evaluating means generatesaid third or fourth signal. With this measure it is assured that whenthe DC offset is so large, in positive or negative direction, that adangerous situation either for the amplifier or for the load or even forthe environment may be feared, an alarm is activated, which is eitheraudible or visible or both.

[0009] In the arrangement of the invention it may occur that a DC offsetexists within the offset detection system itself, especially in theanalog to digital converter. This is of course undesirable because theresult would be that a DC offset across the output terminals of theamplifier is generated in stead of reduced. In order to avoid thissituation the balanced transformer-less amplifier of the presentinvention may still further be characterized in that the outputterminals are connected to the analog to digital converter through apolarity reversing analog switch and that the output of the analog todigital converter is connected to the integrating counter through apolarity reversing digital switch which runs synchronously with thepolarity reversing analog switch at a rate which is an integer multipleof the rate at which the counter results are generated. In this way, anyfault in the count originating from the DC-offset of the analog todigital converter is compensated by an equal but opposite fault in thecount before the predetermined count period is finished.

[0010] Often audio systems have two amplifiers for the left and rightaudio signals or four amplifiers for left and right signals and frontand rear signals. In such case each of the amplifiers should have itsown offset detection means. In order to avoid too much circuitry andconsequently too much chip area when the amplifiers are integrated on asingle monolithic chip, it is a further object of the invention toprovide a plurality of balanced transformer-less amplifiers which ischaracterized in that one or more parts of the offset detection systemare multiplexed to operate successively for the offset detection andcorrection of each of said amplifiers.

[0011] The invention relates also to an offset detection and correctionsystem for use in a balanced transformer-less amplifier according to theinvention. It may be observed, that the offset detection and correctionsystem and the balanced transformer-less amplifier, when they areimplemented in separate integrated circuits, may be easilyinterconnected because the amplifier-terminals, to which the offsetdetection and correction system has to be connected, i.e. the two outputterminals and the input terminal, are usually accessible.

[0012] The invention will be further explained with reference to theattached figures. Herein shows:

[0013]FIG. 1 a first embodiment of a balanced transformer-less amplifierwith an offset detection system according to the invention,

[0014]FIG. 2 a second embodiment of a balanced transformer-lessamplifier with an offset detection system according to the invention and

[0015]FIG. 3 a plurality of balanced transformer-less amplifiers with anoffset detection system according to the invention.

[0016]FIG. 1 shows a balanced transformer-less amplifier A to which aninput signal may be applied through an input terminal I_(n) and a DCseparation capacitor C. Output terminals O of the amplifier are directlyconnected to a load L, which may e.g. be constituted by a loudspeaker.Due to leakage of the capacitor C or due to a not perfectly balancedamplifier A, an undesired DC offset may exist between the two outputterminals and this DC offset may cause a relatively large DC currentflowing through the load L, which usually has a low impedance for directcurrent. This current causes extra dissipation in the load L and in theamplifier A, it reduces the linear range of the amplifier so that signaldistortions at large signal levels easier occur and it may even causedamages of the amplifier and/or of the load.

[0017] In order to correct the DC offset, the amplifier comprises DCoffset detection and correction means D. These means measure the entirevoltage (AC and DC) between the two output terminals, detect the DCoffset contained therein and finally apply the result of this detectionto the input of the amplifier in order to correct or at leastsubstantially reduce the DC-offset. The means D comprise an attenuatorA_(t) to which the output signal of the amplifier is applied and theattenuated signal is subsequently applied to an analog to digitalconverter A_(d). The attenuator A_(t) serves to adapt the level of theoutput signal to the range of operation of the analog to digitalconverter A_(d). The digital output of the converter is subsequentlycounted during a predetermined counting period T_(c) in an integrationcounter C_(i). The analog to digital converter is in the form of asynchronous sigma delta modulator which generates a 1-bit bitstream.This kind of analog to digital converter is preferred because the bitsof the bitstream can be directly applied to the counter C_(i). In thisbitstream the density of the one-bits is proportional to the inputsignal, so that, when the input signal is maximally negative, the sigmadelta modulator generates exclusively zero-bits and when the inputsignal is maximally positive, the sigma delta modulator generatesexclusively one-bits. When the input signal is zero the modulatorproduces equal numbers of one-bits and zero-bits. The sigma deltamodulator may conveniently produce e.g. 625 kbits per second and thecounting period T_(c) may be chosen equal to T_(c)=2¹⁷/625000 s=209,7152ms. In this case the output of the counter is a digital number rangingfrom 0 to 2¹⁷ while the mid-value, which occurs when the input signal iszero during the entire counting period, is equal to 2¹⁶=65536.

[0018] The DC offset detection and correction means D further compriseevaluation means E, wherein the number outputted by the counter C_(i) isevaluated and which in turn controls an 8 bit correction counter C_(c).The output number of this counter is, after conversion in a digital toanalog converter D_(a), applied through a connection V to the input ofthe amplifier A for correcting the DC offset of this amplifier.

[0019] In operation, when the output number of the integrating counterC_(i) is above a first threshold, which lies somewhat above themid-value of 65536, the evaluation means send a down-command to thecorrection counter C_(c). This down-command decreases the value of thecorrection counter by e.g.1 so that, after the DA-conversion, the DClevel at the input of the amplifier A, and thus the DC offset at itsoutput terminals, is reduced by one step. When during the next countingperiod T_(c) the output of the counter C_(i) is still above said firstthreshold, another down-command is send by the evaluation means to thecorrection counter and the DC offset is again reduced by one step, andso on until the counter output is below the first threshold.

[0020] On the other hand, when the output number of the counter C_(i) isbelow a second threshold which is somewhat below the mid-value of 65536,the evaluation means generate an up-command for the correction counterC_(c) and the DC level at the input of the amplifier is increased by onestep. It will be appreciated that, when the counter output number isbetween the first and second thresholds, the counter output number isclose to its mid-value and the DC offset is zero or so low that nocorrection is required.

[0021] Additionally, when the output number of the integration counterC_(i) is above a third threshold which is substantially higher than thefirst threshold, or when the output number is below a fourth thresholdwhich is substantially lower than the second threshold, this means thatat the amplifier output a so large positive or negative DC offset existsthat a dangerous situation may arise. In these cases, the evaluationmeans E send an alarm signal to alarm means A₁ which then may give avisible or audible alarm and/or which may switch off the amplifier fromits power supply, so that any damage of the amplifier or its load isavoided.

[0022] A modification of the arrangement of FIG. 1 has been shown inFIG. 2 in which corresponding elements have the same references. Aproblem with the arrangement of FIG. 1 is that the analog part of theoffset detection and correction system, i.e. the attenuator A_(t) andthe digital to analog converter A_(d) are themselves not free from DCoffset (herein called: system-offset). The offset detection andcorrection system will try to cancel the entire DC offset andconsequently it will create an offset at the output terminals O whichcounteracts the system-offset. To remove this effect the arrangement ofFIG. 2 comprises a polarity reversing analog switch S_(a) before theattenuator A_(t) and a polarity reversing digital switch S_(d) after theanalog to digital converter A_(d). The switches S_(a) and S_(d) runsynchronously with a duty cycle of 50% and at a rate which is an integertimes the rate at which the count results are generated. With otherwords: an integer number of switch cycles (e.g. 4) fit within thepredetermined counting period T_(c) and the switches are equally long inone position as in the other position. The result is that any excessnumber of one-bits, generated by the analog to digital converter due tothe system-offset, is followed by an equal excess number of zero-bitsdue to this offset during the same counting period. Therefore, theoutput number of the counter C_(i) is not any more affected by thesystem-offset. It may be noted that, when the analog to digitalconverter generates a 1-bit bitstream, as is the case with a sigma deltamodulator, the polarity reversing digital switch S_(d) may be formed bya simple EXOR-gate.

[0023] The arrangement of FIG. 3 comprises four BTL amplifiers A₁ to A₄,each with its input capacitance C₁ to C₄ and its load L₁ to L₄. Fordetecting and correcting the DC offset it would be possible to give eachamplifier its own DC offset detecting and correction system. However, inorder to save chip area, the four amplifiers utilize in succession thesame attenuator A_(t), analog to digital converter A_(d), integrationcounter C_(i) and evaluation means E. To this end the output terminalsO₁ to O₄ of the four amplifiers A₁ to A₄ are connected to the attenuatorA_(t) by means of an analog multiplexing switch M₁ and the output of theevaluation means E is connected to four correction counters C_(c1) toC_(c4) through a digital multiplexing switch M₂. The multiplexingswitches M₁ and M₂ run synchronously to connect the units A_(t), A_(d),C_(i) and E firstly between the output terminals O₁ and the input ofC_(c1), then between the output terminals O₂ and the input of C_(c2) andso on. Therefore, the units A_(t), A_(d), C_(i) and E operate insuccession for each of the amplifiers to increment or decrement theirrespective correction counter. Preferably the multiplexing rate ischosen so that the units A_(t), A_(d), C_(i) and E operate for oneamplifier during one single counting period T_(c).

[0024] Additionally, also the DA converter is used in common for theoffset correction of each of the four amplifiers by means of a digitalmultiplexing switch M₃ between the correction counters C_(c1) to C_(c4)and the input of the DA converter and by means of a synchronouslyrunning analog multiplexing switch M₄ between the output of the DAconverter and four current memories M_(e1) to M_(e4). These currentmemories supply the calculated quantized DC current through the leads V₁to V₄ to each of the inputs of the amplifiers A₁ to A₄ in order tocorrect for their respective offsets. The current memories are necessaryto maintain the DC levels when the DA converter is operative for one ofthe other amplifiers. An implementation of the current memories may befound in Section 6.8 of the book “Integrated Analog to Digital andDigital to Analog Converters” by R. van de Plassche, ISBN 0-7923-9436-4.

[0025] It may be noted that the units A_(t), A_(d), C_(i) and E may bemultiplexed without the digital to analog converter being multiplexedand that the digital to analog converter may be multiplexed without theunits A_(t), A_(d), C_(i) and E being multiplexed. It is also noted thatthe multiplex switches M₃ and M₄ need not necessarily run synchronouslywith the multiplex switches M₁ and M₂. It will be apparent that themultiplexing functions, as explained with reference to FIG. 3, and thezeroing of the system-offset which is depicted in FIG. 2, may be used incombination. In that case the functions of the polarity switch S_(a) ofFIG. 2 and the multiplex switch M₁ of FIG. 3 may conveniently becombined.

1. A balanced transformer-less (BTL) amplifier with output terminals forestablishing a DC-connection to a load, comprising an offset detectionsystem (D) for detecting a differential DC-offset across the outputterminals (O), characterized in that said offset detection system (D)comprises an analog to digital converter (A_(d)) to convert the signalvoltage across the output terminals into a digital signal, a counter(C_(i)) integrating the digital signal during a predetermined period oftime (T_(c)), evaluation means (E) for evaluating the result of saidcounter and a digital to analog converter (D_(a)) to generate, inresponse to the output of the evaluation means, an analog correctionsignal which is applied to the input of the amplifier for counteractingthe DC-offset across the output terminals.
 2. A balancedtransformer-less amplifier as claimed in claim 1, characterized in thatthe analog to digital converter (A_(d)) is a sigma-delta modulatorgenerating a 1-bit digital representation of the signal voltage acrossthe output terminals (O) of the amplifier.
 3. A balancedtransformer-less amplifier as claimed in claim 1, characterized in thatthe evaluation means (E) are arranged to generate a first signal whenthe result of the counter (C_(i)) is above a first predetermined leveland a second signal when the result of the counter (C_(i)) is below asecond predetermined level, which is lower than the first level, in thata correction counter (C_(c)) is provided which is decremented by apredetermined number when the evaluating means generate the first signaland which is incremented by said predetermined number when theevaluation means generate the second signal and in that the output ofthe correction counter (C_(c)) is applied to said digital to analogconverter (D_(a)).
 4. A balanced transformer-less amplifier as claimedin claim 3, characterized in that the evaluation means (E) are furtherarranged to generate a third signal when the result of the counter isabove a third predetermined level, which is higher than the first leveland a fourth signal when the result of the counter is below a fourthpredetermined level, which is lower than the second level and that alarmmeans (A₁) are provided which are actuated when the evaluating meansgenerate said third or fourth signal.
 5. A balanced transformer-lessamplifier as claimed in claim 1, characterized in that the outputterminals (O) are connected to the analog to digital converter through apolarity reversing analog switch (S_(a)) and that the output of theanalog to digital converter (A_(d)) is connected to the integratingcounter (C_(i)) through a polarity reversing digital switch (S_(d))which runs synchronously with the polarity reversing analog switch at arate which is an integer multiple of the rate at which the counterresults are generated.
 6. A plurality of balanced transformer-lessamplifiers (A₁ . . . A₄) with an offset detection system (D) as claimedin one or more of the preceding claims, characterized in that one ormore parts of the offset detection system are multiplexed to operatesuccessively for the offset detection and correction of each of saidamplifiers.
 7. An offset detection and correction system for use in abalanced transformer-less amplifier as claimed in one or more of thepreceding claims.